1. Field of the Technology
The present invention relates generally to the field of integrated circuits. More particularly, the present invention relates to the field of signal sensing in memory circuits.
2. Description of the Related Art
A static random access memory (SRAM) is generally implemented as an array of memory cells arranged electrically as a matrix of rows and columns, with a memory cell at each row/column intersection. Each memory cell stores a bit. A column of memory cells is prepared for a read operation by pre-charging the line connecting all cells in that column (e.g., a bit line) to a predetermined level. A selected memory cell is read by activating a line connecting all the memory cells in that row. The selected memory cell is read when the activated word line turns on an access transistor connecting the memory cell to the pre-charged bit line. Depending on the binary state stored in the memory cell, the memory cell will either discharge the bit line through the access transistor (if the stored binary state is low), or will leave the bit line charged (if the stored binary state is high). A sense gate (e.g., a logic gate such as a NAND gate) whose input is connected to the bit line is used to sense the detected state. If the bit line remains charged, the input of the logic gate remains unchanged, as does its output. However, if the bit line is discharged, when the voltage level on the bit line drops below the input threshold of the sense gate, the output of the sense gate will change (the input threshold is the voltage at the gate's input that causes the gate's output to transition). The state of the output of the sense gate indicates the binary state that was stored in the selected cell. Depending on the organization of the array, multiple cells on a row may be read at the same time when their common word line is activated, first by pre-charging all their respective bit lines and then by sensing their individual effect on their associated bit lines through individual sense gates. The amount of time that it takes for a bit line to discharge down to the input threshold of the sense gate is a limiting factor on how quickly a bit cell may be read, and therefore a limiting factor on the speed of the memory device.
Due to the close proximity of a word line and a bit line at the point where they cross each other in the matrix pattern, when a word line is activated by quickly raising the voltage on the word line from low to high, a portion of this rapidly increasing voltage on the word line may be capacitively coupled through to the bit line, thereby temporarily raising the voltage seen on the bit line. This in effect increases the pre-charged level of the bit line. An immediately subsequent discharge of the bit line (e.g., during a read operation) must therefore start from a higher initial voltage, requiring a longer time to discharge down to the input threshold of the sense gate. This discharge time limits the minimum time required for a read operation, which limits the maximum speed at which the memory may operate. Thus the use of a word line to activate the reading of a memory cell may inadvertently cause the read operation to take more time and negatively impact overall memory speed. One approach to resolving this problem is to configure the bit line as a differential pair (two bit lines per column, the stored state is indicated by which one discharges), so that the coupled increase is seen as a common mode voltage and does not affect the sensing speed. However, this requires extra circuitry, which increases manufacturing costs and circuit complexity and limits the amount of memory that may be placed into a given physical area.